This application claims the benefit of Korean Patent Application No. 2001-87518, filed on Dec. 28, 2001, which is hereby incorporated by reference for all purposes as if fully set forth herein.
1. Field of the Invention
The present invention relates to liquid crystal display (LCD) devices. More particularly, the present invention relates to an array substrate for LCD devices having a structure where a breakage of a line is minimized and a signal can flow even when the line is broken. The present invention also relates to a fabricating method for producing such an array substrate.
2. Discussion of the Related Art
Generally, a conventional liquid crystal display (LCD) device uses optical anisotropy and polarization properties of liquid crystal molecules. The liquid crystal molecules have a definite orientational order in alignment resulting from their thin and long shapes. The alignment direction of the LC molecules can be controlled by applying an electric field to the liquid crystal molecules. In other words, as the alignment direction of the electric field is changed, the alignment of the liquid crystal molecules also changes. Since the incident light is refracted based on an orientation of the liquid crystal molecules, due to the optical anisotropy of the aligned liquid crystal molecules, an intensity of the incident light can be controlled.
The LCD devices include upper and lower substrates, where color filters and thin film transistors (TFTs) are respectively disposed. The upper and lower substrates are referred to as a color filter substrate and an array substrate, respectively. A liquid crystal layer is interposed between the upper and lower substrates. The liquid crystal layer is driven by an electric field between a common electrode and a pixel electrode. The LCD devices have a high transmittance and a high aperture ratio.
Recent research has been devoted to, active matrix LCD devices, where TFTs and pixel electrodes, connected to the TFTs, are disposed in a shape of matrix. FIG. 1 is a schematic perspective view of an active matrix liquid crystal display (AM-LCD) device, in accordance with the related art.
In FIG. 1, the AM-LCD device 11 includes upper and lower substrates 5 and 22, and a liquid crystal layer 14 interposed therebetween. The upper substrate 5 includes a black matrix 6, a color filter layer 8 and a common electrode 18. The lower substrate 22 includes a pixel electrode 17 at a pixel region “P” and an array line having a TFT “T.” Each TFT “T” functions as a switching device, is disposed in a matrix, and is connected to a gate line 13 and a data line 15. The pixel region “P” is defined by a cross of the gate line 13 and the data line 15. The pixel electrode 17 at the pixel region “P” is made of a transparent conductive material such as indium-tin-oxide (ITO) of high transmittance. A gate pad 24 and a data pad 26 having a specific area are formed at one end of the gate line 13 and the data line 15, respectively. An external signal is applied to each pad 24 and 26, and transmitted to the TFT “T” through each line.
FIG. 2 is a flow chart illustrating a conventional fabricating process of a liquid crystal cell. In step st1, a lower substrate is prepared by forming an array of TFTs and pixel electrodes corresponding to the TFTs on the lower substrate.
In step st2, an orientation film is formed on the lower substrate. Formation of the orientation film includes depositing a polymeric thin film on the lower substrate and subsequently performing a rubbing process. The polymeric thin film is deposited on the lower substrate with a uniform thickness. The rubbing process is also uniform. The rubbing process determines an initial alignment direction and enables normal operation of the liquid crystal layer and the uniform display characteristic of the LCD device. Typically, an organic material of the polyimide series is used as the orientation film. The rubbing process includes rubbing the orientation film in a specific direction with a rubbing cloth, thereby aligning the liquid crystal molecules along, or in, the rubbing direction.
In step st3, a seal pattern is formed on the lower substrate. For each liquid crystal cell, the seal pattern serves two functions: forming a gap for liquid crystal material injection and confining the injected liquid crystal material. The seal patterning process forms a desired pattern by the application of a thermosetting plastic. A screen-printing method, using a screen mask, is typically used for this process.
In step st4, a spacer is sprayed on the lower substrate. The size of the spacer used in the liquid crystal cell maintains a precise and uniform gap between the upper and lower substrates. Accordingly, the spacers are uniformly sprayed on the lower substrate. The spacer spray method can be divided into two different types: a wet spray method that involves spraying a mixture of alcohol and spacer material, and a dry spray method that involves spraying spacer material alone.
In step st5, the upper and lower substrates are aligned and attached.
In step st6, the attached liquid crystal substrates are divided into unit cells. Generally, a plurality of unit cells are formed on a large sized glass substrate, and then divided through a cutting process. In the fabrication process of the initial LCD devices, the unit cells are separated after simultaneous injection of the liquid crystal material into the unit cells. However, injection of liquid crystal material is commonly performed after a large sized liquid crystal substrate is cut into unit cells due to an increase in the cell size.
In step st7, a liquid crystal material is injected into the unit cells. The unit cell has a size of several hundred square centimeters with a gap of several micrometers. Accordingly, a vacuum injection method using a pressure difference between the interior and exterior of the unit cell is commonly used as an effective injection method.
In step st8, a portion of the upper substrate is cut to expose a driving portion on the lower substrate. This step is referred to as a scribe/break process. In the scribe/break process, a breakage of a line on the lower substrate often occurs.
FIG. 3 is a schematic plan view of the AM-LCD device of FIG. 1. As previously discussed, the AM-LCD device 11 includes the upper and lower substrates 5 and 22. Each gate line 13 has an associated gate pad 24 at one end, and is formed along a first direction on the lower substrate 22. Each data line 15 has an associated data pad 26 at one end, and crosses the gate lines 13, thereby defining a matrix of pixel regions “P”. Also, the transparent pixel electrodes 17 are formed at the pixel regions “P.” Each TFT “T” includes a gate electrode 30, an active layer 32, and source and drain electrodes 36 and 38. Each TFT “T” is connected to one of the gate lines 13 and one of the data lines 15.
Since an external signal is directly applied to each pad 24 and 26 of a driving region “D,” each pad 24 and 26 is exposed. An additional gate pad terminal 60 and an additional data pad terminal 62 are formed to minimize an influence resulting from an external environment and prevent a bad contact between an external signal line and each pad 24 and 26. The gate pad 24 is connected to the gate line 13 through a gate link line 42 and the data pad 26 is connected to the data line 15 through a data link line 46. The hatched region shows a portion of the upper substrate 5 where the black 6 matrix is formed. The upper substrate 5 is cut to expose the driving region “D” of the lower substrate 22 through the scribe/break process illustrated in step st8.
FIGS. 4A to 4C are schematic cross-sectional views showing a fabricating process of an array substrate for the related art AM-LCD device 11. FIGS. 4A to 4C are taken along the line IV—IV of FIG. 3.
In FIG. 4A, the gate line 13 (of FIG. 3), the gate link line 42 and the gate pad 24 are formed on the lower substrate 22 through depositing and patterning one of a conductive metal group, including aluminum (Al) and aluminum alloy of low resistance. The gate line 13 (of FIG. 3) is disposed along a first direction and the gate link line 42 is extended from the gate line 13 (of FIG. 3). The gate pad 24 is formed at one end of the gate link line 42. Here, the gate line 13 (of FIG. 3) including the gate electrode 30, the gate link line 42 and the gate pad 24 are about 2700 in height. Next, a gate insulating layer 31, a first insulating layer, is formed on an entire surface of the lower substrate 22 through depositing one of an inorganic insulating material group including silicon nitride (SiNx) and silicon oxide (SiO2). The gate insulating layer 31 is about 4000 in height.
In FIG. 4B, an active layer 32 and an ohmic contact layer 34 of an island shape are sequentially formed on the gate insulating layer 31 over the gate electrode 30. Generally, the active layer 32 is made of amorphous silicon including hydrogen (a-Si:H) and the ohmic contact layer 34 is made of impurity-doped amorphous silicon including n-type or p-type impurities. Next, the source and drain electrodes 36 and 38 are formed on the ohmic contact layer 34 through depositing and patterning one of a conductive metal group including chromium (Cr), tungsten (W), molybdenum (Mo) and titanium (Ti). The data line 15, connected to the source electrode 36, is formed at the same time. The data link line 46 is connected to the data line 15, and the data pad 26 is formed at one end of the data link line 46. Here, the data line 46 including the data pad 26 and the data link line 46 are about 1500 in height. The source and drain electrodes 36 and 38 arc spaced apart from each other. The ohmic contact layer 34 between the source and drain electrodes 36 and 38 is etched so that the active layer 32 is exposed. The exposed active layer 32 functions as a channel where carriers of the source and drain electrodes 36 and 38 are transmitted. Next, a passivation layer 50 is formed on an entire surface of the lower substrate 22 through depositing one of a transparent organic insulating material group including benzocyclobutene (BCB), acrylic resin. The passivation layer 50 is about 2000 in height. The passivation layer 50 has a drain contact hole 52 exposing the drain electrode 38, a gate pad contact hole 54 exposing the gate pad 24, and a data pad contact hole 56 exposing the data pad 26.
In FIG. 4C, the pixel electrode 17, contacting the drain electrode 38, is formed at the pixel region “P” through depositing and patterning one of a transparent conductive metal group including indium-tin-oxide (ITO) and indium-zinc-oxide (IZO). Simultaneously, the gate pad terminal 60 and the data pad terminal 62 of an island shape are formed. The gate pad terminal 60 and the data pad terminal 62 contact the gate pad 24 and the data pad 26, respectively.
In the related art AM-LCD device 11, a cutting line for the upper substrate 5 crosses the gate link line 42 and the data link line 46. Since the gate insulating layer 31 and the passivation 50 layer over the gate link line 42 have a total height are totally of about 6000, the gate link line 42 is not very influenced by a pressure exerted by a cutting device. On the other hand, since the passivation layer 50 over the data link line 46 is only about 2000 in height, the data link line 46 may be scratched or damaged along a portion under the cutting line. Further, the data link line 46 may be broken.